The Instruction Set of the 80X86 family is broken up into the following sets:

1. Arithmetic
2. ASCII-BCD Conversion
3. Bit Shifting
4. Comparison
5. Data Transfer
6. Flag Operations
7. Input/Output
8. Logical Operations
9. Looping
10. Processor Control
11. Stack Operations
12. String Operations
13. Transfer (Conditional)
14. Transfer (Unconditional)
15. Type Conversion
 

Operands

An operation can have zero one or two operands in an 80X86 instruction.

The general form of an instruction is

        operation operand1,operand2

where operand1 is the destination and operand2 is the source.
 

The types of operands are

1. Register

     MOV AX,DX

2. Immediate

    MOV AX, 25

3. Direct Memory

    MOV AX,FLDDW1
 

4. Indirect memory

    MOV BX, OFFSET FLDDW1
    MOV [BX],0   ; Move a zero nto FLDDW1
 

5. Address Displacement

    MOV AX,[BX]
    MOV AX,FLDDW1[BX]
 

The MOV INSTRUCTION

 Syntax:

[label:]     MOV register/memory,register/memory/immediate
 

Example:

  MOV AX,25

  MOV DX,AX

  MOV WORDVAL[BX],25
 

The MOV instruction transfers data referenced by the address operand2 to the address referenced by operand1. You can move a byte, word, or a doubleword. Memory to memory moves are not allowed. Immediate to segment or segment to segment are also not allowed.
 

MOVE-AND-FILL INSTRUCTION 80386 and above only

Syntax:

[label:]    MOVSX/MOVZX  register/memory,register/memory/immediate

These commands allow the movement of byte or word to word or doubleword. The left-most bits of the destination are filled with zeros. MOVSX is for signed arithmetic values and MOVZX is for unsigned numeric values. Note the length of an immediate operand cannot exceed the length defined by the first operand.
 

THE XCHG INSTRUCTION
 

Syntax:

[label:] XCHG register/memory, register/memory

Example:

        XCHG    CL, BH
        XCHG    CX,WORDQ

The XCHG instruction exchanges the data in operand1 and operand2.
 

THE LEA INSTRUCTION
 

Syntax:

[label:]     LEA register ,memory

Example:    LEA  BX, FLDDW1   ;  Same as  MOV BX, OFFSET FLDDW1

This instruction loads the effective address or the offset address of operand2 into operand1. This instruction is used to initialize the BX, DI, or SI registers for indexing an address in memory.
 

    DATABLK     DB     20 DUP (?)
    SAVBYTE     DB      ?

        ...
    LEA     BX,DATABLK         ;Load offset of DATABLK
    MOV     SAVBYTE,[BX]     ;Move first byte of DATABLK ;to SAVBYTE
 

THE INC AND DEC INSTRUCTION

Syntax:

[label:]     INC/DEC     register/memory

Example:
              INC    BX

These instructions increment or decrement the operand. The result of the operation may clear or set the OF,SF, and ZF flags.
 

THE ADD AND SUB INSTRUCTIONS

[label:]    ADD/SUB    register/memory, register/memory/immediate

Valid operations involve register to/from register, register to/from memory, immedkiate to/from register, and immediate to/from memory. Flags affected are AF, CF, OF, PF, SF, and ZF.
 

Example:
        ADD    AX,CX
        ADD    EBX,DBLWORD
        SUB    BL, 10
 

THE INT INSTRUCTION
 

The INT instructions provides the program access to the BIOS and DOS interrupt tables in low memory. When an INT is executed the following takes place:

1. Decrements the stack point by 2 and pushes the content of the flags register onto the stack.
2. Clears the interrupt and trap flags.
3. Decrements the SP by 2 and pushes the CS register onto the stack.
4. Decrements the SP by 2 and pushes the IP onto the Stack.
5. Causes the required operation to be performed.

To return from the interrupt, the routine issues an IRET (interrupt return), which pops the registers off the stack and returns to the instruction immediately following the INT in your program.
 

ADDRESSING MODES

The three basic modes of addressing are Register, Immediate, and Memory.
Memory addressing consists of six types, for eight modes in all.

1.  Register Addressing

     MOV    DX, CX    ;register to register move

2. Immediate Addressing

    MOV    DL,10        ;immediate to register move

3. Direct Memory Addressing

    MOV    DL,COUNT    ;memory to register move

4. Direct-Offset Addressing

    MOV    CL, KBNAME + 2
    MOV    CL, KBNAME[2]

5. Register Indirect Memory Addressing - Uses the base registers (BX and BP) and index registers
    (DI and SI), coded with brackets which indicates a reference to memory.  If you code .386, .486, or
    .586 directive, you can use any of the general purpose registers (EAX, EBX, ECX, and EDX) for
     indirect addressing.

    LEA        BX, DATA_VAL
    MOV       [BX],CL

6. Base Displacement Addressing - Uses the base registers (BX and BP) and the index registers
    (DI and SI) plus a displacement ( a number or an offset value) to form an effective address.

    MOV    CL,[DI + 12]
    MOV    CL,LIST[DI]

7. Base-Index Addressing

    MOV    AX,[BX+SI]    ;These two are the same
    MOV    AX,[BX][SI]

8. Base-Index with Displacement Addressing

    MOV    AX,[BX + SI + 2]
    MOV    AX, LIST[BX + DI]

THE SEGMENT OVERRIDE PREFIX

The processor automatially selects the appropriate segment when addressing:

    CS:IP for fetching an instruction,
    DS:offset for accessing data in memory,  and
    SS:SP for accessing the stack.

You can override the conventional segment references by using the : operator
Example:

        MOV    DX, ES:[BX]    ;Move to DX from ES:[BX]  (indirect memory reference in ES)
 

NEAR AND FAR ADDRESSES

A near address consists of only the 16-bit offset of an address.  A near reference is always within the segment.

A far address consists of a 32-bit offset.  A far reference can be any segment.

ALIGNING DATA ADDRESSES
 

To speed up processor performance data should be aligned on memory unit word sizes.

Example:

    An 8086 and 80286 have 16-bit data buses.  If data is aligned on a WORD boundary then only one access is necessary to obtain a full word.  If data was algined on a BYTE boundary then some words would require two accesses to obtain the whole word.

    For the 80386 and above alignment should be on double word boundaries since the memory word size is 32-bits.